Since computer processors with caches were first combined into multiprocessor systems there has been a need for cache coherence. More recently cache coherent multiprocessor systems have been implemented in systems-on-chips (SoCs). The cache coherent systems in SoCs comprise instances of processor intellectual properties (IPs), memory controller IPs, and cache coherent system IPs connecting the processors and memory controllers. More recently some SoCs integrate other agent IPs having coherent caches, such as graphics processing units, into heterogeneous multiprocessor systems. Such systems comprise a single centralized monolithic cache coherent system IP.
In the physical design of such SoCs, the centralized cache coherent system IP is a hub of connectivity. Wires connect transaction interfaces of each agent with the coherence system IP and from that to the memory controller IP. Such an arrangement causes an area of significant congestion for wire routing during the physical design phase of the chip design process.